1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory device which is capable of quickly erasing the entire content of a large-capacity memory like a bit-map format picture memory for example.
2. Description of the Prior Art
Conventionally, bit-map format picture memories are widely made available for processing graphic picture signals or controlling the character-writing position.
Generally, these conventional bit-map format picture memories are provided with a substantial capacity because of the need for providing siubstantial memory area that is enough to accommodate a page-full dot data of picture information.
Typically, as shown in FIG. 1, these conventional picture memories are provided with 1M byte memory capacity by applying 4 units of banks 1 through 4, each being comprised of a plurality of 256k-bit dynamic RAMs for example, in which banks 1 through 4 are respectively in connection with commonly-available address lines A0 through A8 and data lines DO0 and DO7 and DI0 through DI7. In addition, these banks 1 through 4 are also connected to the control-signal transmission line via a bank-selecting means 5.
FIG. 2 is the circuit diagram of a conventional bank-selecting means 5. Decoder 6 decodes the upper bits A18 and A19 of address signals to selectively allow one of NAND gates 15 through 18 to open itself so that the control signals comprised of RAS (Row Address Strobe) signal, CAS (Column Address Strobe) signal, and WE (Write Enable) signal can selectively be delivered to whichever of those banks 1 through 4.
When either the power of the picture memory is on or a new picture data is written into it, the content of old data in memory should be erased.
The picture memory content is erased by writing memory area. When erasing the data content stored in the picture memory by applying conventional bank-selecting means shown in FIG. 2, the designated data are written into the picture memory by each byte by sequentially designating addresses. After completing the writing of needed data into picture memory bank 1, the data are sequentially written into banks 2 through 4, thus eventually requiring the conventional memory system to spend much time before fully erasing the data content stored in these picture-memory banks 1 through 4.
As shown in FIG. 1, any of those large-capacity picture memories is mostly comprised of a dynamic RAM. However, in order to access the dynamic RAM within the shortest period of time, access operation requires delicate coordination with the refreshing cycles of the dynamic RAM itself. Since erasure of the memory content lasts for a long period of time, extreme complexity is needed for designing the access timing.
In particular, reflecting such an extremely large capacity of the picture memory, the saving of time to be spent for erasure of memory content is a critical problem in dealing with any picture-processing apparatus featuring high resolution like a laser printer for example.